IEEE

A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC With On-Chip Bit-Weight Calibration

Abstract: This article presents a single-channel 13-bit pipelined successive-approximation register (SAR) analog-to-digital converter (ADC). To achieve energy-efficient residue amplification, a ring ...
GitHub

PSoC™ 6 MCU: SAR ADC simultaneous sampling

This code example demonstrates simultaneous sampling of two SAR ADCs. This code example is supported on devices such as PSoC™ 62 MCU (CY8C62x4) which has two SAR ADCs. The two SAR ADCs are configured ...
IEEE

A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator

Abstract: This paper presents a 1-GS/s 7-bit 3-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). To strike a good balance among the noise performance, power ...
GitHub

zf_driver_adc.hpp

#define ADC_CH0_PATH "/sys/bus/iio/devices/iio:device0/in_voltage0_raw" #define ADC_CH1_PATH "/sys/bus/iio/devices/iio:device0/in_voltage1_raw" #define ADC_CH2_PATH ...