Electronics For You

Accelerating RISC-V Verification With Quality And Security At The Core

As the RISC-V ecosystem grows, startups struggle to verify complex chips before tape-out. Chennai-based startup addresses ...
EDN

Leveraging system models for RTL functional verification

Register transfer level (RTL) verification remains the bottleneck in digital hardware design. Industry surveys show that functional verification accounts for 70 percent of the total design effort. Yet ...
EDN

RTL prototyping: a hardware/software co-verification solution

Traditional ASIC and IP verification methods cannot adequately exercise the hardware and software components of today's designs. This is due to tool performance limitations, which impose a bottleneck ...
Electronic Design

Hybrid Emulation Accelerates Architecture Optimization, Software Development, And Software-Driven Verification

Mobile and Internet of Things (IoT) devices and their supporting infrastructure are driving the system-on-chip (SoC) design challenge with demanding specifications, increasing software content, and ...
Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...