Hackaday

32C3: A Free And Open Source Verilog-to-Bitstream Flow For ICE40 FPGAs

[Clifford] presented a fully open-source toolchain for programming FPGAs. If you don’t think that this is an impressive piece of work, you don’t really understand FPGAs. The toolchain, or “flow” as ...
Hackaday

FPGAs In C With Cynth

Programming an FPGA with Verilog looks a lot like programming. But it isn’t, at least not in the traditional sense. There have been several systems that aim to take C code and convert it into a ...
Design-Reuse

FPGA Prototyping as a Verification Methodology

To some degree, FPGA prototyping has become commonplace in the majority of SoC development programs. This paper is a brief discussion of four aspects of this type of approach. First the forces behind ...
EDN

FPGA design and verification solutions from Lattice and Aldec

The folks at Lattice Semiconductor and Aldec have announced a new OEM agreement that will deliver the only OEM FPGA mixed language simulator. Active-HDL Lattice Edition will be bundled with Lattice's ...
Design-Reuse

Lattice and Aldec Announce New Alliance For FPGA Design And Verification

Simulator Delivers Industry Leading Speed, and is the Only OEM Mixed Language Simulator for FPGA Design HILLSBORO, OR - April 21, 2008 - Lattice Semiconductor Corporation (NASDAQ: LSCC) and Aldec, ...
EDN

Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code

HDL Coder generates target independent, synthesizable Verilog and VHDL code from MATLAB functions, Simulink models, and Stateflow charts. The generated HDL code is bit-true and cycle-accurate to ...
Electronics Weekly

FPGA verification for DO-254 is in the hardware

Verifying a complex FPGA design under DO-254 guidelines for use in safety- and mission-critical airborne systems is not without its challenges. Louie De Luna, Aldec Europe’s Product Manager for DO-254 ...