Remember how I said that Moore's Law is "the full-employment act for computer pundits"? In the smaller niche of microprocessor journalism, there used to be another topic that was always good for a ...

A new instruction set by the original creator of MIPS aims to reinvent the ultra-low power, high-efficiency processor -- and to do so with an architecture that's fundamentally open and available to ...

Ten years ago, I waded into the then-raging “Mac vs. PC” wars with a lengthy treatise on “RISC vs. CISC: the Post-RISC Era.” In the conclusion to that article, I declared the “RISC vs. CISC” debate ...

Try to investigate the differences between the x86 and ARM processor families (or x86 and the Apple M1), and you'll see the acronyms CISC and RISC. It's a common way to frame the discussion, but not a ...

RISC-V architecture is gaining traction in China as a geopolitically neutral alternative to x86 and ARM architectures dominated by the U.S. The rise of RISC-V presents a potential risk to Advanced ...

MIPS Technologies released details this week of the latest incarnation of the architecture that defined RISC at a time when the rest of the industry was fully engaged in CISC architecture processors.

RISC is a somewhat misleading term, as a RISC processor doesn't *have* to have fewer instructions in its ISA than a CISC system (Though RISC architectures do tend to try to do so). For example, the ...

The processor we will be considering in this tutorial is the MIPS processor. The MIPS processor, designed in 1984 by researchers at Stanford University, is a RISC (Reduced Instruction Set Computer) ...